View ICS952302_289273.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS952302
Frequency Generator for Transmeta Efficeon
Recommended Application: Transmeta Efficion, ATi M6 Output Features: * 3 - CPUs @ 3.3V including 1 free running CPUCLK_F * 7 - PCI @ 3.3V, including 4 free running PCICLK_F * 1 - 27MHz clock @ 3.3V * 2 - 48MHz clocks @ 3.3V * 2 - REF clocks @3.3V Key Specifications: * CPU output jitter: < 250ps * PCI output skew: < 250ps * CPUT - PCI output skew: 1-3ns * 27MHz Accuracy < 50ppm * 48MHz Accuracy < 50ppm
TM
TM
Features: * Support I2C Index read/write and block read/write operations. * Uses external 14.318MHz referience input or XTAL. * Full Load Power consumption reduced >10% compared to reference device * Power management via SMBus
Functionality
Byte 4b7 0 0 0 0 1 1 1 1 Byte 4b6 0 0 1 1 0 0 1 1 Byte 4b5 0 1 0 1 0 1 0 1 Spread %
Pin Configuration
VDDREF 1 REF0 2 GNDREF 3 X1 4
PCICLK1 11 PCICLK_F2 12 PCICLK_F3 13 VDDPCI 14 PCICLK2 15 GNDPCI 16 N/C 17 N/C 18 VDDCOR 19 PCI_STOP# 20 **PD# 21 GND48 22 SDATA 23 SCLK 24
ICS952302
+/-0.3 +/-0.6 +/-0.25 +/-0.45 -0.60% -1.20% -0.50% -0.90%
CENTER
X2 5 VDDPCI 6 PCICLK_F0 7 PCICLK_F1 8 GNDPCI 9 PCICLK0 10
DOWN
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
REF1 VDDCPU N/C CPUCLK0 GNDCPU CPUCLK1 CPUCLK_F CPU_STOP# GND N/C OE* N/C VDD N/C VDD27 GND 27MHZ N/C N/C N/C GND48 VDD48 48MHZ_1 48MHZ_0
48-TSSOP
* Internal Pull-Up Resistor **No Diode Clamp to VDD
0957B--10/05/04
ICS952302
Pin Descriptions
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 PIN NAME VDDREF REF0 GNDREF X1 X2 VDDPCI PCICLK_F0 PCICLK_F1 GNDPCI PCICLK0 PCICLK1 PCICLK_F2 PCICLK_F3 VDDPCI PCICLK2 GNDPCI N/C N/C VDDCOR PCI_STOP# **PD# GND48 SDATA SCLK 48MHZ_0 48MHZ_1 VDD48 GND48 N/C N/C N/C 27MHZ GND VDD27 N/C VDD N/C OE* N/C GND CPU_STOP# CPUCLK_F CPUCLK1 GNDCPU CPUCLK0 N/C VDDCPU REF1 PIN TYPE PWR OUT PWR IN OUT PWR OUT OUT PWR OUT OUT OUT OUT PWR OUT PWR N/C N/C PWR IN IN PWR I/O IN OUT OUT PWR PWR N/C N/C N/C OUT PWR PWR N/C PWR N/C IN N/C PWR IN OUT OUT PWR OUT N/C PWR OUT DESCRIPTION Ref, XTAL power supply, nominal 3.3V 14.318 MHz reference clock. Ground pin for the REF outputs. Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Power supply for PCI clocks, nominal 3.3V Free running PCI clock not affected by PCI_STOP# . Free running PCI clock not affected by PCI_STOP# . Ground pin for the PCI outputs PCI clock output. PCI clock output. Free running PCI clock not affected by PCI_STOP# . Free running PCI clock not affected by PCI_STOP# . Power supply for PCI clocks, nominal 3.3V PCI clock output. Ground pin for the PCI outputs No Connection. No Connection. 3.3V power for the PLL core. Stops all PCICLKs at logic 0 level, when low. Free running PCICLKs are not effected by this input. Asynchronous active low input pin, with 120Kohm internal pull-up resistor, used to power down the device. The internal clocks are disabled and the VCO and the crystal are stopped. Ground pin for the 48MHz outputs Data pin for SMBus circuitry, 5V tolerant. Clock pin of SMBus circuitry, 5V tolerant. 48MHz clock output. 48MHz clock output. Power pin for the 48MHz output.3.3V Ground pin for the 48MHz outputs No Connection. No Connection. No Connection. 27.0000MHz Video Clock for ATi Chipset Ground pin. Power pin for the 27MHz output.3.3V No Connection. Power supply, nominal 3.3V No Connection. Active high input for enabling Memory Channel outputs. 0 = tri-state outputs, 1= enable outputs No Connection. Ground pin. Stops all CPUCLK, except those set to be free running clocks Free running CPU clock. Not affected by the CPU_STOP#. CPU clock outputs. 3.3V Ground pin for the CPU outputs CPU clock outputs. 3.3V No Connection. Supply for CPU clocks, 3.3V nominal 14.318 MHz reference clock.
* Internal Pull-Up Resistor
** No diode clamp to VDD.
0957B--10/05/04
2
ICS952302
General Description
Spread spectrum may be enabled through SMBus programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS952302 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Block Diagram
(1:0)
1
27MHz
(1:0)
1
(1:0)
(2:0)
4
(3:0)
PD# OE
0957B--10/05/04
3
ICS952302
SMBus Table: Output Control Register Byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name CPUCLK_F CPUCLK0 CPUCLK1 27MHZ 48MHZ_0 48MHZ_1 REF0 REF1 Control Function Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1
42 45 43 32 25 26 2 48
SMBus Table: Output Control Register Byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name PCICLK_F0 PCICLK_F1 PCICLK_F2 PCICLK_F3 PCICLK0 PCICLK1 PCICLK2 Spread Spectrum Mode Control Function Test Mode Output Enable Output Enable Output Enable Spread Control Output Enable Output Enable Spread Control for PLL1 Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable OFF 1 Enable Enable Enable Enable Enable Enable Enable ON PWD 1 1 1 1 1 1 1 0
7 8 12 13 10 11 15
-
SMBus Table: Output Control Register Byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Pin # 42 45 43 (note) Name CPUCLK_F CPUCLK0 CPUCLK1 Control Function Allow assertion of CPU_STOP# or setting of CPU_STOP control bit in SMBus register to stop CPU clocks Type RW RW RW 0 Free Running Free Running Free Running 1 Stoppable Stoppable Stoppable Disable I2C PWD 0 1 1 x x 1 x 1
Reserved Reserved RW Reserved Reserved RW CPU_STOP Stop all CPU clocks RW Enable Reserved Reserved RW CPU_STOP# 20, 41 Bit 0 H/w or S/w Select RW H/W PCI_STOP# Note: Byte2bit2=0 (Enable) to stop all CPUCLK's ONLY when Byte2 bit(5:7) at STOPPABLE MODE SMBus Table: Output Control Register Byte 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0957B--10/05/04
Pin #
Name PCICLK_F0 PCICLK_F1 PCICLK_F2 PCICLK_F3 PCICLK0 PCICLK1 PCICLK2 PCI_STOP
Control Function Allow assertion of PCI_STOP# or setting of PCI_STOP control bit in SMBus register to stop PCI clocks Stop all PCI clocks
Type RW RW RW RW RW RW RW RW
0 Free Running Free Running Free Running Free Running Free Running Free Running Free Running Enable
1 Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable Disable
PWD 0 0 0 0 1 1 1 1
7 8 12 13 10 11 15
-
4
ICS952302
SMBus Table: Spread Spectrum Control Register Byte 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Spread Position SS1 SS2 Control Type Function Center or Down SS RW Spread Bit 1 RW Spread Bit 2 RW Reserved Reserved Reserved Reserved Reserved 0 Center 1 Down PWD 1 0 0 -
See SS Table
SMBus Table: Control Register Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Control Function Type Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 1 PWD -
SMBus Table: Control Register Byte 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Control Function Type Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 1 PWD -
SMBus Table: Vendor & Revision ID Register Byte 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 Control Function REVISION ID Type R R R R R R R R 0 1 PWD x x x x 0 0 0 1
VENDOR ID
0957B--10/05/04
5
ICS952302
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . 5.5 V GND -0.5 V to VDD +0.5 V 0C to +70C 115C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Input Capacitance1 Clk Stabilization1 Skew1
1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD(op) IDDPD Fi CIN CINX TSTAB TCPU-PCI VIN = VDD
CONDITIONS
MIN 2 VSS - 0.3
TYP
MAX VDD + 0.3 0.8 5
UNITS V V mA mA mA
VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = (full load); 66MHz CL = 0 pF; With input address to Vdd or GND VDD = 3.3 V; Logic Inputs X1 & X2 pins From VDD = 3.3 V to 1% target Freq. VT = 1.5 V
-5 -200 102 320 11 14.3132 150 600 16 5 27 3 1 1.5 45 5.5 4
mA A MHz pF pF ms ns
Guaranteed by design, not 100% tested in production.
0957B--10/05/04
6
ICS952302
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS IOH = -20 mA VOH2B Output High Voltage VOL2B IOL = 12 mA Output Low Voltage VOUT = 1 V IOH2B Output High Current VOUT = 3.135V VOUT = 1.95 V IOL2B Output Low Current VOUT =0.4V 1 tr2B VOL = 0.4 V, VOH = 2.4 V Rise Time tf2B VOH = 2.4 V, VOL = 0.4 V Fall Time1 1 dt2B VT = 1.5 V Duty Cycle 1 tsk2B VT = 1.5 V Skew 1 tjcyc-cyc2B VT = 1.5 V Jitter, Cycle-to-cycle
1
MIN 2.4
-23 27 1 1 45
TYP 2.9 0.25 -67 -8 56 23 1.4 1.4 51.5 60 175
MAX 0.4 -29
UNITS V V mA mA ns ns % ps ps
30 2 2 55 175 250
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK, PCICLK_F
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS VOH2B IOH = -20 mA Output High Voltage IOL = 12 mA VOL2B Output Low Voltage VOUT = 1 V IOH2B Output High Current VOUT = 3.135V VOUT = 1.95 V IOL2B Output Low Current VOUT =0.4V tr2B VOL = 0.4 V, VOH = 2.4 V Rise Time1 tf2B VOH = 2.4 V, VOL = 0.4 V Fall Time1 1 dt2B VT = 1.5 V Duty Cycle 1 tsk2B VT = 1.5 V Skew 1 tjcyc-cyc2B VT = 1.5 V Jitter, Cycle-to-cycle
1
MIN 2.4
-23 27 1 1 45
TYP 2.9 0.25 -67 -8 56 23 1.3 1.2 50.5 68 100
MAX 0.4 -29
UNITS V V mA mA ns ns % ps ps
30 2 2 55 250 250
Guaranteed by design, not 100% tested in production.
0957B--10/05/04
7
ICS952302
Electrical Characteristics - 27MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS FACC Frequency Accuracy REF Out = 14.31818MHz IOH = -20 mA VOH2B Output High Voltage VOL2B IOL = 12 mA Output Low Voltage VOUT = 1 V IOH2B Output High Current VOUT = 3.135V VOUT = 1.95 V IOL2B Output Low Current VOUT =0.4V tr2B VOL = 0.4 V, VOH = 2.4 V Rise Time1 tf2B VOH = 2.4 V, VOL = 0.4 V Fall Time1 1 dt2B VT = 1.5 V Duty Cycle 1 tjcyc-cyc2B VT = 1.5 V Jitter, Cycle-to-cycle
1
MIN -50 2.4
-23 27 1 1 45
TYP 0 2.9 0.25 -67 -8 56 23 1.1 1.2 51 340
MAX 50 0.4 -29
UNITS ppm V V mA mA ns ns % ps
30 2 2 55 400
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) CONDITIONS REF Out = 14.31818MHz IOH = -20 mA IOL = 12 mA VOUT = 1 V IOH2B Output High Current VOUT = 3.135V VOUT = 1.95 V IOL2B Output Low Current VOUT =0.4V tr2B VOL = 0.4 V, VOH = 2.4 V Rise Time1 tf2B VOH = 2.4 V, VOL = 0.4 V Fall Time1 1 dt2B VT = 1.5 V Duty Cycle 1 tjcyc-cyc2B VT = 1.5 V Jitter, Cycle-to-cycle 1 Guaranteed by design, not 100% tested in production. PARAMETER Frequency Accuracy Output High Voltage Output Low Voltage SYMBOL FACC VOH2B VOL2B MIN -50 2.4 TYP 0 2.9 0.25 -67 -8 56 23 1.1 1.5 52 200 MAX 50 0.4 -29 UNITS ppm V V mA mA ns ns % ps
-23 27 1 1 45
30 2 2 55 350
0957B--10/05/04
8
ICS952302
Electrical Characteristics - REF
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10 - 30 pF (unless otherwise stated) CONDITIONS REF Out = 14.31818MHz IOH = -20 mA IOL = 12 mA VOUT = 1 V IOH2B Output High Current VOUT = 3.135V VOUT = 1.95 V IOL2B Output Low Current VOUT =0.4V tr2B VOL = 0.4 V, VOH = 2.4 V Rise Time1 1 tf2B VOH = 2.4 V, VOL = 0.4 V Fall Time 1 dt2B VT = 1.5 V Duty Cycle 1 tjcyc-cyc2B VT = 1.5 V Jitter, Cycle-to-cycle 1 Guaranteed by design, not 100% tested in production. PARAMETER Frequency Accuracy Output High Voltage Output Low Voltage SYMBOL FACC VOH2B VOL2B MIN -50 2.4 TYP 0 2.9 0.25 -67 -8 56 23 1.3 1.7 53 270 MAX 50 0.4 -29 UNITS ppm V V mA mA ns ns % ps
-23 27 1 1 45
30 2 2 55 500
0957B--10/05/04
9
ICS952302
General SMBus serial interface information for the ICS952302 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P
0957B--10/05/04
Not acknowledge stoP bit
10
ICS952302
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
0957B--10/05/04
11
ICS952302
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 4 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CLK_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLK
PCICLK VCO Crystal
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS952302 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
0957B--10/05/04
12
ICS952302
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CLK_STOP# is synchronized by the ICS952302. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
INTERNAL CPUCLK PCICLK CLK_STOP# PCI_STOP# (High)
CPUCLK _F
Notes: 1. All timing is referenced to the internal CPU clock. 2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS952302. 3. CLK_STOP# signal. 4. All other clocks continue to run undisturbed.
0957B--10/05/04
13
ICS952302
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS952302. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS952302 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only three rising PCICLK clocks, off latency is one PCICLK clock.
CPUCLK (Internal)
PCICLK_F (Internal) PCICLK_F (Free-running) CLK_STOP#
PCI_STOP#
PCICLK
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS952302 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS952302. 3. All other clocks continue to run undisturbed. 4. CLK_STOP# is shown in a high (true) state.
0957B--10/05/04
14
ICS952302
N
c
L
INDEX AREA
E1
E
12 D
a
A2 A1
A
In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS 0 8 0 8 aaa -0.10 -.004 VARIATIONS N 48
10-0039
-Ce
b SEATING PLANE
D mm. MIN MAX 12.40 12.60
D (inch) MIN .488 MAX .496
aaa C
Ref erence Doc.: JEDEC Publication 95, M O-153
(0.020 mil) (240 mil) 6.10 mm. Body, 0.50 mm. pitch TSSOP
Ordering Information
ICS952302yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0957B--10/05/04
15

▲Up To Search▲

Price & Availability of ICS952302

	To Download ICS952302 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .